ication group．abc: a system for sequential synthesis and verification．december 2005 release．http://www-cad.eecs.berkeley.edu/~alanmi/abc．

[5] j. cong and y. ding, “flowmap: an optimal technology mapping algorithm for delay optimization in lookup-table based fpga designs”, ieee trans．cad, vol. 13(1), january 1994, pp. 1-12．

[6] iwls 2005 benchmarks．http://iwls.org/iwls2005/benchmarks.html．

[7] s. yang．logic synthesis and optimization benchmarks. version 3.0．tech. report. microelectronics center of north carolina, 1991．

[8] the sis group．berkeley logic interchange format (blif)．university of berkeley,

july 1992．

[9] joachim pistorius, mike hutton, alan mishchenko, robert brayton．benchmarking method and designs targeting logic synthesis for fpgas．university of berkeley, 2007．

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